1. Field of the Invention
The present invention relates to an image processing system, and more particularly, to an apparatus and method for controlling data writing and/or reading by mapping luminance components and chrominance components into different structures so that the number of required cycles and the amount of data to be fetched can be reduced when data is accessed in a memory in a burst mode.
2. Description of the Related Art
Among image processing systems, H.264 or MPEG-4 advanced video coding (AVC) decoder is a standard technology formulated in a joint video team (JVT) that is a cooperative project of international standard organizations, ISO/IEC MPEG and ITU-T VCEG (Refer to “Text of ISO/IEC FDIS 14496-10: Information Technology—Coding of audio-visual objects—Part 10: Advanced Video Coding”, ISO/IEC JTC 1/SC 29/WG 11, n5555, March 2003). This was developed with an aim of improving encoding efficiency more than double those of MPEG-1, MPEG-2, MPEG-4 Part 2 encoding standards of the existing ISO/IEC organization and H.261, H.262 (MPEG-2), and H.263 of the ITU organization. In order to improve encoding efficiency, improved technologies different from conventional video compression methods were provided here. Among the technologies, as representative ones, there are an inter prediction technology using multiple reference frames and a variable block size, and a context adaptive binary arithmetic coding (CABAC) technology, a 4×4 integer transform, or a deblocking filter.
However, since these technologies for improving encoding efficiency increase greatly the complexity of a codec compared to the conventional methods, it is difficult for these technologies to obtain the competitiveness of a hardware chip solution for high definition (HD) image services. For example, in order to decode an HD format bitstream with 1920×1080i@60 Hz, a specification with level 4.0 or 4.1 or higher is required. Here, levels 4.0 and 4.1 relate to the limits of bitrates of an input bitstream, and an input of up to 24 Mbps in level 4.0 and 60 Mbps in level 4.1 can be processed. If a pipeline processing in units of macroblocks is enabled in a memory chip, approximately 4.084 μsec will be taken to process one macroblock. The number of cycles required for processing one macroblock varies with respect to operational frequencies to be employed.
Meanwhile, when inter prediction for one macroblock is performed in a prediction module among elements of the H.264 or MPEG-4 AVC decoder and the size of a block processed is small, a memory should be accessed many times to obtain a prediction block and also many adjacent pixels should be accessed such that the delay increases greatly.